The invention relates to a charge coupled device of the buried channel type with a semiconductor body comprising a first layer of a first conductivity type which adjoins a surface of the body and which forms a buried channel for storage and transport of electric charge, a second layer of the second conductivity type opposite to the first which lies below and adjoins the first layer and forms a barrier layer, and a third layer of the first conductivity type which lies below and adjoins the second layer and through which excess charge can be drained from the first layer, the surface being provided with a system of electrodes with a series of gates which are situated above the buried channel and which are connected to a voltage source for the at least temporary application of such a voltage to the gates that an inversion layer of the second conductivity type adjoining the surface is formed below the gates, while means are present for obtaining a built-in potential difference in the channel whereby potential wells in which charge can be stored alternating with potential barriers are formed in the channel upon the application of equal voltages to the gates. The invention also relates to a charge coupled image sensor comprising such a charge coupled device.
Such a device is known inter alia from U.S. Pat. No. 5,115,458. This describes an image sensor of the n-channel type comprising channels in the form of n-type surface zones provided in a p-type region (well) which is formed at the surface of an n-type substrate and which separates the channels from the substrate. It is known that in such a configuration any excess charge in the channels, consisting of electrons, can be drained off through the substrate. A major advantage of this vertical charge drain which can be mentioned is that it prevents the "blooming" effect which occurs upon overexposure. In addition, it is possible to set the charge state to zero at the beginning of an integration period (charge reset) in that all charge present in the image sensing elements is removed through the substrate, whereby it is possible, for example, to adjust the exposure time. The surface is provided with a system of electrodes comprising gate electrodes or gates which are insulated from the surface by a thin gate dielectric. Voltages are applied to the gates, at least during the integration period, such that inversion of the conductivity type occurs at the surface. This operating mode, also called "all gates pinning mode" (AGP), renders it possible to suppress to a substantial degree the dark current which is largely determined by the surface states, and thus in particular to eliminate largely the unpleasant influence of local defects which manifest themselves as white spots during display. In order to obtain sufficiently large charge packages per pixel also in the AGP mode, the known device is provided with means for optimizing the potential profile in the channel whereby, in the case of charge transport from left to right, a potential barrier and a potential well are formed below a portion of the gate adjoining the left-hand edge of each gate and the remaining portion of the gate, respectively. In the device described in the cited U.S. Pat. No. 5,115,458, these means are formed by a doping profile in the channel. Instead of this, other means known per se such as a profile in the thickness of the gate dielectric, or combinations of different means may be used. The device of U.S. Pat. No. 5,115,458 is operated as a two-phase device in the transport phase.
As will become evident from the description of the Figures, the present invention is based inter alia on the recognition that the two-phase operational mode leads to a limitation in the quantity of electric charge to be processed, and thus to a comparatively low signal-to-noise ratio. Since further details will be given below with reference to the drawings, a summary description only is given here of the effects which play a pan in the known device for an understanding of the invention. An n-type channel device is described here, but it will be perfectly obvious that an analogous description may be given for a p-type channel device.
In an n-type channel CCD, clock voltages are applied to the gates with a first, high level at which electric charge (electrons) is stored below the gates, and with a second, low level at which potential barriers are formed below the gates. Both the high and the low level are subject to stringent limitations; the high level must not be higher than the voltage at which punch-through takes place between the channel and the n-type substrate. At a higher gate voltage, charge can flow from the substrate into the channel; the low level is preferably not chosen to be lower than the threshold voltage so as to prevent inversion or at least deep inversion from occurring at the surface during transport. Such inversion in general leads to a reduction in the charge storage capacity and an increase in the parasitic gate capacitance, and thus to a possible delay during transport. These limitations of the clock voltages have consequences for the means by which the potential profile of wells and barriers is formed, i.e. the difference between well and barrier must remain so low that no potential barriers which hamper the charge transport are formed at the given clock voltage levels. This means in practice that the differences between potential wells and potential barriers become very small in the integration periods in which the entire integrating surface is in the inverted state, so that also the charge packages formed in the potential wells are very small. An increase in the size of the packages through an increase in the said potential difference is not possible owing to the problems during charge transport caused thereby and described above.